1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device with a double-gate structure.
2. Background Art
For scaling down the physical dimension of MOS transistors, lower power and higher speed, double-gate transistors, for example, FinFET have been proposed (see Japanese Patent Laid-Open Publication No. 2005-294789, for example).
This structure has following advantages.
(1) The structure with two gates reduces the short channel effect and the punch through leakage between the source and the drain.
(2) The small effective electric field in the direction vertical to the channel can improve the carrier mobility.
(3) The off current is reduced. Therefore, the channel width (fin height or number of fins) can be increased accordingly, and thus, the current can be increased.
Furthermore, there has been proposed the Schottky source/drain transistor technique in which the source region and the drain region of a transistor are formed by a metal layer instead of an impurity diffusion layer (see Jakub Kedzierski et al., IEDM Technical digest, pp. 57-60, (2000), for example).
In this structure, the parasitic resistance is reduced in the source region and the drain region, and a shallow junction (Schottky junction) is formed.
In addition, since no impurity is used in the source and the drain, the high-temperature heat treatment for activation is not necessary. Therefore, the manufacturing process can be substantially simplified, and the LSI manufacturing cost can be reduced.
Furthermore, there is a Schottky barrier at the end of the source. Therefore, the off current can be reduced, and the short channel effect can be suppressed (the transistor can be downsized).
In particular, in the case of a Ge channel transistor, the solid solubility of the dopant is low, and the dopant is likely to diffuse. Therefore, the Schottky junction is preferable for the source/drain structure.
However, this transistor has a problem that the Schottky contact resistance (the interface resistance of the silicon/silicide or the metal) has to be reduced.
One solution to this problem is a work function control technique for the source/drain material. For example, a metal or silicide (ErSi2, for example) with a low work function for the source and drain of an nMOS transistor and a metal or silicide (PtSi, for example) with a high work function for the source and drain of a pMOS transistor have been proposed (see Jakub Kedzierski et al., IEDM Technical digest, pp. 57-60, (2000), for example).
According to this technique, the Schottky barrier height of the nMOS transistor can be reduced to about 0.28 eV, and the height of the Schottky barrier of the PMOS transistor can be reduced to about 0.22 eV.
That is, in the nMOS transistor and the pMOS transistor, metal silicide source and drain having a relatively low Schottky contact resistance can be formed.
However, it is not enough to provide a sufficiently high current, and the Schottky barrier height has to be further reduced.
Besides, it is difficult to further reduce the Schottky barrier height only by controlling the work function of the metal, because of the Fermi-level-pinning effect.
Thus, there has been proposed a combination technique using strained channel and Schottky junction. This is a technique that uses a strain (mechanical stress) to reduce the Schottky barrier height and the contact resistance (see A. Yagishita, T-J. King, and J. Bokor, “Schottky Barrier Height Reduction and Drive Current Improvement in Metal Source/Drain MOSFET with Strained-Si Channel”, Jpn. J. Appl. Phys., Vol. 43, No. 4B, pp. 1713-1716, (2004), for example).
Furthermore, another technique, channel strain engineering, has been developed to improve the carrier mobility. For a planar pMOSFET, a compressive strain applied from SiGe embeded into the source and drain regions is effective. For a planar nMOSFET, it is known that it is effective to apply, to the channel, a tensile strain from SiC embeded into the source region and the drain region or a tensile strain from a film with a tensile strain deposited on the gate, the source and the drain.
As described above, according to the conventional techniques (the strained channel technique and the Schottky source/drain technique), in the case of the nMOS transistor, a tensile strain is used, so that the mobility is improved, and the Schottky barrier height is reduced.
That is, the driving current of the Schottky source/drain nMOS FinFET can be increased by a simple combination of conventional techniques.
However, according to the conventional techniques described above, a compressive strain is used for the pMOS transistor, and therefore, the Schottky barrier cannot be reduced, although the carrier mobility can be improved.
Thus, the driving current of the Schottky source/drain pMOS FinFET cannot be increased.